1. Technical Field
The present invention relates, generally, to testing and burn-in of semiconductor devices and, more particularly, to an improved test and burn-in fixture for use with bare die and high-density packages such as ball grid arrays.
2. Background Information
Modern semiconductor fabrication techniques have dramatically increased the density and speed of semiconductor devices, leading to a parallel effort in the field of semiconductor packaging, where increased device density gives rise to many challenges related to electrical connectivity, heat-transfer, manufacturability, and the like. One such challenge relates to the burn-in and testing of ball-grid array (BGA) packages, chip-scale packages (CSP), bumped die, and other such devices using an array of solder balls as contacts.
With such devices, edge-of-package to solder ball location is a critical dimension, and is easily influenced by substrate tolerance issues, processing machinery, test machinery, and other factors. The BGA ball pad location tolerance might be approximately +/−25 microns, while the singulation tolerance of the edges of finished devices may vary by +/−50 microns. Any such errors in alignment may result in erroneous rejection due to poor contacts during electrical tests—errors which will only become more significant as ball pitch becomes smaller and effects such as thermal expansion and the like become more and more dominant.
Furthermore, while ball-grid array patterns may be standardized, the dimensions of the packages or die themselves often vary greatly. Referring to FIG. 1, for example, while the two BGA devices 102 and 106 exhibit the same pattern of solder balls 104, their external package or die dimensions are different, and would therefore require different test adapters for burn-in or functional testing. Specifically, the distance x′ from corner 116 to ball 114 on device 106 is significantly larger than dimension x from corner 112 to ball 110 on device 102. Similarly, the dimension y′ of device 106 is greater than dimension y of device 102. Traditional BGA test systems would rely on registration of the external package of the devices to corners within a rectangular fixture. As a result, any fixture designed for use with device 102 could not be used with device 106.
Similarly, any wafer-level testing would require refixturing of the test board to accommodate different die geometries. As it is desirable to achieve 100% utilization of burn-in boards, current test systems are inadequate in that rejects during wafer-level testing can not easily be removed after each stage.
Methods are therefore needed in order to overcome these and other limitations of the prior art.